Since the introduction of the personal computer (PC) architecture in 1981 and the ubiquitous PC-AT (advanced technology) architecture in 1984, PC-based computer systems have been continuously evolving. A concurrent evolution has likewise occurred with processors and operating systems. Although dramatic advancements have been made in each of these areas, the evolution process has been somewhat restricted due to legacy provisions. The legacy provisions result, in part, from the widespread popularity of PC's, which represent the vast majority of computers used worldwide. It is estimated that upwards of 100 million PC's are sold per year.
To better understand the reason for legacy provisions, consider that the PC-AT architecture is an open architecture, allowing literally 10's of thousands of peripheral components and software applications to be used on a PC-AT-based platform. Now consider the aspect of add-on peripherals. The PC-AT architecture introduced the industry standard architecture (ISA) bus and corresponding ISA expansion slots. Expansion slot architecture has evolved to include such variants as EISA (Enhanced ISA), microchannel (MC), ISA plug-n-play, and PCI (Peripheral Component Interconnect), the current de-facto standard.
The original PCI architecture was designed to solve several problems. The explicit purpose of the PCI design was to provide a standardized architecture that would simplify chipset and motherboard designs. It also was designed to improve data transfer rates. Furthermore, it provided an abstraction mechanism that enabled transparent support of legacy components. In fact, PCI is more of an interconnect (hence the name) standard than an expansion bus standard.
A key tenant of the PCI design is processor independence; that is, its circuits and signals are not tied to the requirements of a specific microprocessor or family. The design provides interconnects between various disparate bus types using bridges. A bridge may also be used to couple a pair of PCI buses. For the user, bridges are generally an invisible interface between two bus systems. The PCI architecture also decouples processor memory subsystems from subordinate buses, enabling a processor and a bridge to operate in parallel.
In order to increase efficiency of the PCI bus(es), bridges usually employee buffering to facilitate long data transfers (data streams). To support this capability, the architecture provides intelligent read and write buffers in a PCI bridge. The read buffers are commonly referred to as pre-fetch buffers, which are also known as delayed transaction buffers.
Although this burst access capability can be used to greatly increase transfer rates, the original design was targeted at transfer of single-channel data streams. As a result, recently introduced multi-function PCI devices that support multiple-channel data streams are restricted in their transfer rates. In fact, in many instances the aggregate transfer rate of all channels for a multi-function PCI device is actually less than the single channel rate for the same device.